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The average hyperscale data center operator today faces a paradox written in kilowatts: the demand for AI compute is doubling faster than the electrical grid can keep pace. Every megawatt of headroom spent on brute-force GPU arrays leaves less room for the dense, parallel workloads that enterprise AI actually runs most of the time. That tension is precisely what Intel addressed at Computex 2026 when it formally launched the Xeon 6+ processor family and demonstrated that Intel packed an astonishing 36,864 Cores Into Racks no taller than 32U.
That number is worth highlighting. In a single liquid-cooled rack with a 100-kilowatt power budget, you get 36,864 processing threads. These are ready to handle agent tasks, manage context windows, and run policy logic all at once. This isn’t just a prototype it’s production hardware available now from Dell Technologies, Hewlett Packard Enterprise, Lenovo, and Supermicro.
What the Intel Xeon 6+ Architecture Actually Is
The Xeon 6+ Architecture isn’t made from a single chip. Instead, Intel created “Clearwater Forest” as one of its most complex chiplet assemblies ever. The package brings together 12 compute chiplets built on the Intel 18A node, 3 active base tiles on Intel 3, and 2 I/O tiles on Intel 7. These are connected by a high-bandwidth on-chip fabric and stacked using Foveros Direct 3D. EMIB bridges link the tiles in a 2.5D setup.
Each compute tile has twenty-four Darkmont efficiency cores. The top Xeon 6990E+ model combines 12 of these tiles in a single socket, giving a total of 288 cores. This flagship pairs the 288 E-cores with an all-core turbo speed of up to 2.8 GHz, a 576 MB shared L3 cache (2 MB per core), and a default TDP of 450 watts, with a lower-power 330-watt mode also available.
The 18A Process Breakthrough
The underlying silicon is just as important as architecture. Intel 18A is the company’s most advanced manufacturing process, using gate-all-around RibbonFET transistors and PowerVia backside power delivery. This is the first time both have been used together in a commercial data center CPU. The node was developed and is produced in the U.S. at Intel’s Fab 52 in Chandler, Arizona, which matters for American companies concerned about supply chain risks after recent chip shortages.
The Intel 18A manufacturing process is more than merely a name. Ericsson’s tests showed that a single 288-core Xeon processor cut runtime rack power by 38 percent and delivered over 60 percent better performance per watt compared to older Sierra Forest systems. For operators with thousands of servers, a 38 percent power reduction doesn’t just lower electricity costs—it changes what’s possible in data center design.
The 36,864-Core Rack: Specifications and Context
The headline figure Intel Packed 36,864 Cores Into Racks emerges from a specific reference design announced at Computex with the processor launch. Both reference designs can support up to 128 Intel 128-core Granite Rapids Xeon 6 or 288-core Clearwater Forest Xeon 6+ processors. This totals between 16,384 P-cores and 36,864 E-cores, plus up to 384 TB of DDR5 memory, all within a 100 kW power envelope.
Three hundred and eighty-four terabytes of DDR5 memory in one rack. That figure matters almost as much as the core count, because modern Disaggregated Inference architectures are memory-bound long before they become compute-bound. The Intel Xeon 6 plus processor data center server rack specifications include twelve-channel DDR5 memory with scalable bandwidth for high-density systems, alongside 96 lanes of PCIe Gen 5 and CXL support to accelerate data movement across heterogeneous infrastructure.
To show how competitive Intel’s position is, Arm is developing two rack-scale reference designs for agentic workloads using its new AGI CPUs. One is a 36 kW air-cooled system with 8,160 cores, and the other is a 200 kW liquid-cooled rack with 45,696 cores. Intel’s design comes close to Arm’s larger liquid-cooled setup yet remains within a 100 kW power limit, which most co-location facilities can handle today without needing a special power contract.
Agentic Density: Why Core Count Has Become the New Metric
Until recently, data center buyers judged server performance by FLOPS (floating-point operations per second), a measure created for training workloads that rely on matrix multiplication on GPUs. Inference workloads, especially those with high Agentic Density, have very different requirements.
Intel pointed out that infrastructure is shifting from a training-focused phase where one CPU usually supports four GPUs to an inference-focused model with nearly a 1:1 ratio of CPUs to accelerators as agentic workloads grow. An AI agent running a think-plan-act-reflect loop spends most of its compute time on context retrieval, policy enforcement, tool execution, memory management, and orchestration. These tasks are better suited to many efficient CPU cores than to a few GPU streaming multiprocessors.
Intel’s approach sees CPUs as orchestration engines rather than just focusing on GPU FLOPS. The Xeon 6+ offers 288 efficient cores and 576 MB of last-level cache in a disaggregated tile design. This setup satisfies the Agentic Density needs of multi-agent systems, where having more cores and cache is most important.
Disaggregated Inference in Practice
Intel didn’t just talk about this vision it showed it in action. The company presented a new enterprise inference cloud from Vector Core Compute, created by Vista Equity Partners and Cambium Capital. This system uses Intel Xeon 6 processors for orchestration and execution, SambaNova RDUs for decoding, and NVIDIA Blackwell GPUs for prefill. The demo showed how Disaggregated Inference can split different stages of AI workload execution across specialized hardware.
The live demo running the MiniMax 2.5 model is just the kind of proof of concept that enterprise architects look for before investing. Together. AI has already become the first commercial customer for Vector Core Compute’s agentic cloud, giving the architecture practical validation only weeks after launch.
What This Means for U.S. Data Center Operators
The link between data center density and grid stability is very real. The U.S. grid is taking on a huge new load from AI infrastructure, with conservative estimates suggesting hyperscale AI power demand could require gigawatts of additional generation capacity in just three years. In this context, fitting more compute into each kilowatt isn’t just marketing it’s a real way to help keep industrial power costs under control.
The new rack design focuses on performance per watt and per dollar rather than just maximizing training throughput. This shows a broader industry shift, as agentic AI places much greater demands on CPUs for orchestration, scheduling, memory management, data movement, and the execution of non-matrix workloads.
Intel’s Xeon 6+ Architecture also introduces Application Energy Telemetry, a real-time energy-monitoring feature that lets operators see exactly which processes are consuming power, down to the job level. For companies focused on sustainability and emissions reporting, this telemetry is as valuable as the efficiency improvements it enables.
The Road Ahead
The Intel 18A manufacturing process is still supply-constrained, so Intel is managing silicon allocations carefully. This should improve as Fab 52 increases its output. In the meantime, Intel has confirmed that Xeon 7 “Diamond Rapids,” the next-generation all-P-core server processor, will launch in 2027 on the improved 18A-P process node. It will feature 16-channel memory, PCI Express 6.0, up to 192 P-cores per socket, and a process refinement that cuts thermal resistance by a third and boosts efficiency by 18 percent at the same clock speeds.
The data center built around the Intel Xeon 6 plus processor data center server rack specifications available today is not an endpoint it is the first generation of infrastructure made for a realm where AI agents, not people, drive most workloads. Operators who plan for Agentic Density now will have the right infrastructure as this shift accelerates. Those who wait for simpler solutions may find themselves constrained by real estate and power contracts that weren’t designed for what lies ahead.
Intel CEO Lip-Bu Tan summed it up at Computex: “Our customers are asking us to think at the system level to help them serve real agentic workloads at scale.” Packing 36,000 cores into a single rack shows what’s possible when system-level thinking and technology come together.
Source: https://newsroom.intel.com/artificial-intelligence/intel-announces-new-ai-innovations-at-computex
