The competition for 2nm chips is between Intel’s 18A, expected in 2025, and Japan’s Rapidus 2HP, planned for 2027. Rapidus is aiming for a higher logic density of 237.31mm2, compared to Intel’s 18A at 184.21 MTr/mm2, and is challenging TSMC. Intel is ahead in timing with its RibbonFET and PowerVR technologies, while Rapidus is using IBM and IMEC technology to move directly to advanced GAA and aims to double production speed.
Key Comparison: Intel 18A vs Rapidus 2HP
- Timeline and production: Intel 18A is expected to begin high-volume production in late 2025, while Rapidus plans to start mass production in 2027.
- Logic density: report indicates that the Rapidus 2HP node may reach 237 MTR/mm2, which could be higher than the reported 184 MTR/mm2 for Intel A and similar to TSMC’s N2 node.
- Tech highlights: Intel users RibbonFET (GAA) and PowerVR for backside power delivery. Rapidus 2HP users gate all around (GAA) transistors and are likely to feature a unique, single-wafer process to reduce production time significantly.
- Strategy: Intel is focusing heavily on performance per watt and utilizing 18A for internal and foundry customers early. Rapidus is a state-backed collaborative effort supported by Toyota, Sony, and NEC, aiming to skip legacy nodes and go straight to TNM to regain Japanese competitiveness.
Race Dynamics
- Rapidus Agility: With its all-single-wafer process, Rapidus aims for a 50-day turnaround, much faster than the industry standard of about 120 days.
- Intel’s early start: By aiming for 2025, Intel will have a significant lead in the 2nm class, also known as the angstrom era, compared to Rapidus.
- 2nm competition: Both Intel and Rapidus are competing with TSMC’s N2 node, which is also expected to launch in 2025.
To summarize, Intel 18A will reach the market first, but Rapidus 2HP could offer higher or at least very competitive logic density when it launches in 2027.
WCCFTech reports that Rapidus is working on its cutting-edge 2nm node called 2HP. This new technology is expected to match the logic density of TSMC’s N2 and surpass Intel’s 18A.
According to the report, Rapidus 2HP is expected to reach a logic density of 237.31 MTR/MM2, which is very close to TSMC’s N2 at 236.17 MTR/MM2. Both nodes use high-density (HD) cell libraries with a 138-unit cell height and a G45 pitch. These setups are designed to maximize logic density and suggest similar transistor counts.
Intel’s 18AN node, despite using a smaller node size, is reported to have a logic density of 184.21 MTR/mm^2, which is lower than that of Intel’s 18AN node. The report says this is partly because Intel uses BS-PDN, which takes up some of the front-side metal layers and lowers the density measured in the HD library. However, Intel focuses more on performance per watt than on raw density since 18A is mainly for internal use.
Lapidus plans to release its 2NM PDK in early 2026 and aims to start mass production in 2027.
WCCF Tech says Rapidus will offer its 2NM PDK to customers in the first quarter of 2026. The company is moving quickly. Tech Power Up reports that Rapidus has already taped out a 2NM GAA test chip and plans to launch high-volume production in 2027. The chip was manufactured using ASML’s EUV tools and has passed initial electrical tests for mass production in 2027. Rapidus’ CEO said the IIM-FAB is expected to produce about 25,000 wafers per month, according to the report.
TechPowerUp also reports that by 2027, Rapidus may be one or two nodes behind TSMC and possibly Intel. To stand out, the company is focusing on agility through a unique all-single wafer process, with a turnaround time of just 50 days, compared to about 120 days for the usual batch-and-single wafer mix.
Source url : Rapidus 2HP Reportedly Surpasses Intel 18A Logic Density Impacted by BSPDN, Rivals TSMC
